1. 高性能低功耗多核处理器及Chiplet设计

2. 基于RISC-V/ARM的SoC设计

3. 图像及语音的人工智能算法及硬件加速器研究

4. 高能效体系架构及三维集成设计

主持多项核高基国家重大专项、科技部重点研发计划、国家自然科学基金等国家级课题。

[1] Zizheng Dong, Qin Wang, Weijia Zhu, Shuaipeng Li, Kunyue Li, Sai Gao, Naifeng Jing, JianfeiJiang. DIONet3D: Dual-Input Dual-Output Deep Neural Network with 3D-Enhanced PDN Featurefor IR Drop Prediction in 3D ICs[J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. (TCAD 2026)

[2] Ji, S., Yang, W., Jiang, J., Jing, N., Jiang, H., Mao, Z., & Wang, Q. MACS: A Multi-Domain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD 2025)

[3] Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng,Jianfei Jiang, Zhigang Mao. A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip[J]. IEEE Transactions on Very Large Scale Integration Systems,2025, 33(6): 1502-1515 (TVLSI 2025)

[4] Wanqi Chen, Weidong Yang, Yiming Guo, Jing Qiu, Renpei Wang, Jianfei Jiang, Naifeng Jing and Qin Wang, RVME: An Efficient Matrix Engine Design Based on Matrix Extension of RISC-V , The 43rd IEEE International Conference on Computer Design(ICCD 2025)

[5] Tong Li, Honglan Jiang, Zhou Wang, Qin Wang, Jianfei Jiang, Zhigang Mao. Efficient Extraction and Packing Modules for Posit Multipliers. IEEE Transactions on Circuits and Systems II: Express Briefs, Year: 2025 Volume: 72 Issue: 11(TCAS-II 2025)

[6] Ang Li, Pengyu Liu, Zizheng Dong, Jinhao Li, Jianfei Jiang, Weijia Zhu, Naifeng Jing, Qin Wang. Fine-Grained Modeling and Evaluation of 3D Power Distribution Networks in Logic-on-Memory Stacking Architecture[J]. IEEE Transactions on Signal and Power Integrity, 2025.(TSPI 2025)

[7] D Yu,A Li,N Jing,J Jiang,W Sheng,Q Wang. VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks[C]. Proceedings of the Great Lakes Symposium on VLSI 2024 ACM, 2024: 357-363.（2024 GLSVLSI最佳论文提名）

[8] A. Li, J. Jiang, Q. Wang, N. Jing, Z. Dong, S. Ji, X. Cheng, Y. Zhao, "A Method to Improve 3D Interconnections Resource Utilization and Reliability in Hybrid Bonding Process Considering the Effects on Signal Integrity," 2023 IEEE 73rd Electronic Components and Technology Conference Orlando, FL, USA, 2023, pp. 2131-2136, (ECTC 2023)

[9] Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao:An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 30(11): 1587-1600 (TVLSI 2022)

[10] Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing. Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. Proceedings -Design, Automation and Test in Europe, , 1394-1399.(DATE 2021)

1、国家高层次人才计划（2023年）

2、省部级科技进步二等奖（2022年、2023年）

3、IEEE/ACM  2021DAC System Design Contest 3^rd Place 第三名（2021年）

4、全国工业和信息化技术技能大赛“集成电路 EDA 开发应用赛项”一等奖、优秀教练（2022 年）

5、全国集成电路创新创业大赛全国总决赛一等奖、优秀指导老师（2020年、2021年、2022年）

6、华为杯第二届中国研究生创“芯”大赛华为专项奖一等奖（2019 年）

7、华为杯首届中国研究生创“芯”大赛新思专项奖（2018 年）

8、全国集成电路创新创业大赛全国总决赛特等奖、优秀指导老师（2018 年）

9、上海交通大学优秀教师奖（2011年）

10、上海交通大学“三育人”先进个人（2010年）