蒋剑飞，博士，副研究员，博士生导师，本科毕业于浙江大学，获工学学士学位，研究生毕业于上海交通大学，获电路与系统工学硕士学位，电子科学与技术工学博士学位。获国家留学基金委《青年骨干教师出国研修项目》资助，2013.7-2014.7 期间美国北卡罗莱纳州立大学电子工程系访问学者。获国家外专局资助，2016.10～2016.11期间比利时鲁汶大学和欧洲微电子中心访问学者。

1、2.5D/3D集成芯片

2、SoC体系结构

3、高性能异构计算与神经网络加速电路

主要从事数字集成电路设计领域的研究，研究方向包括2.5D/3D集成芯片、SoC体系结构、高性能异构计算与神经网络加速电路等。承担国家重大专项、国家重点研发等多个重大项目中的芯片课题，在28nm和40nm等工艺下成功流片Logic-on-SRAM三维集成计算芯片、2.5D芯粒接口与集成芯片、粗细混合粒度计算芯片、系列RISC-V SoC人工智能芯片。近年来，在集成电路领域重要期刊会议上发表SCI/EI论文30余篇，授权国家发明专利10多项。

[1] Z Dong, Q Wang, W Zhu, S Li, K Li, S Gao, N Jing, J Jiang*, “DIONet3D: Dual-Input Dual-Output Deep Neural Network with 3D-Enhanced PDN Feature for IR Drop Prediction in 3D ICs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2026.

[2] Z Dong, C Yin, P Liu, S Li, A Li, W Zhu, W He, G He, Q Wang, Y Sun, Z Mao, N Jing*, J Jiang*, “A 51.19 mm², 4 TB/s bandwidth 3D Logic-on-SRAM Stacking CGRA Chip,” IEEE Custom Integrated Circuits Conference (CICC) 2026.

[3] J Sun, L Liu, K Li, S Li, S Gao, Z Dong, J Jiang*, F Wu*, “An Energy Efficient CPU-FPGA Heterogeneous Acceleration System for Third-Generation Genomic Sequencing Based on Minimap2,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2025.

[4] K Li, S Li, X Li, Z Dong, S Gao, J Sun, N Jing, Q Wang, G He, J Jiang*, “Efficient Die-to-Die Communication: UCIe Link Simulation and Optimization in a Chiplet-Based System,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems,2025.

[5] Z Dong, S Li, W Zhu, A Li, Q Wang, N Jing, W Sheng, J Jiang*, “A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2025.

[6] K Li, Z Zhao, Q Cai, Q Wang, N Jing, Z Mao, J Jiang*, “A Novel Vehicle Collision Detection System: Integrating Audio-Visual Fusion for Enhanced Performance,” Expert Systems with Applications, 2024.

[7] L Xie, Z Dong, J Sun, S Gao, S Li, N Jing, Q Wang, J Jiang*, “A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction,” IEEE International Symposium on Circuits and Systems (ISCAS), 2024.

[8] N Jing, Z Zhang, Y Sun, P Liu, L Chen, Q Wang, J Jiang*, “Exploiting Bit Sparsity in Both Activation and Weight in Neural Networks Accelerators,” Integration, the VLSI Journal, 2023.

[9] A Li, J Jiang, Q Wang*, N Jing, Z Dong, S Ji, X Cheng, Y Zhao, “A Method to Improve 3D Interconnections Resource Utilization and Reliability in Hybrid Bonding Process Considering the Effects on Signal Integrity,” IEEE 73rd Electronic Components and Technology Conference (ECTC), 2023.

[10] J Zhang, S Cheng, F Dong, K Chen, Y Qiao, Z Mao, J Jiang*, “A Hierarchical Communication Algorithm for Distributed Deep Learning Training,” IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), 2023.

[11] X Li, Z Dong, S Li, S Gao, J Jiang*, G He, Z Mao, “MUG5: Modeling of Universal Chiplet Interconnect Express (UCIe) Standard Based on gem5,” IEEE 15th International Conference on ASIC (ASICON), 2023. (Excellent Student Paper)

[12] G Deng, Q Wang*, J Jiang*, Q Hong, N Jing, W Sheng, Z Mao, “A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images,” IEEE Geoscience and Remote Sensing Letters, 2022.

[13] J Jiang*, M Jiang, J Zhang, F Dong, “A CPU-FPGA Heterogeneous Acceleration System for Scene Text Detection Network,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2022.

[14] Q Wang, F Shen, L Cheng, J Jiang*, G He, W Sheng, N Jing, Z Mao, “Ship Detection Based on Fused Features and Rebuilt Yolov3 Networks in Optical Remote-Sensing Images,” International Journal of Remote Sensing, 2021.

[15] Q Wang, Z Liu, J Jiang*, N Jing, W Sheng, “A New Cellular-Based Redundant TSV Structure for Clustered Faults,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018.

本科生课程:

数字逻辑/Verilog 硬件描述语言

研究生课程：

SystemVerilog电路设计与验证

竞赛指导：

第八届(2024)全国大学生集成电路创新创业大赛，全国一等奖（企业大奖）

第六届(2022)全国大学生集成电路创新创业大赛，全国一等奖（企业大奖）

第五届(2021)全国大学生集成电路创新创业大赛，全国一等奖

第四届(2020)全国大学生集成电路创新创业大赛，全国一等奖