Fault tolerate architecture, heterogeneous system architecture, and edge computing architecture. Especially focused on application-driven design/architecture innovations, which include novel architectures for artificial intelligence (AI) and acceleration with CPU/GPU/FPGA.

1.焦佳佳, 付宇卓，可靠性感知的片上网络链路管理策略, 上海交大学报47卷第1期, 2013年1月.

2.韩兴，蒋江，付宇卓，动态可重构众核处理器仿真平台设计，上海交大学报47卷第1期, 2013年1月.

3.刘婷，乌耀益，付宇卓，片上网络任务映射算法的可靠性优化，上海交大学报47卷第1期, 2013年1月.

4.Jiao J, Fu Y. RAPA: reliability-aware priority arbitration strategy for network on chip[C]//Proceedings of the great lakes symposium on VLSI. ACM, 2012: 99-102.

5.Yaoyi Wu; Jiang Jiang; Jiajia Jiao; Xing Han, “Fault-Tolerant Flow Control with Dataflow Division in Network-on-Chip,” Fourth International Conference on Computational Intelligence and Communication Networks (CICN), pp.487,490, 3-5 Nov. 2012

6.Jiajia Jiao, Peng Wu, Yuzhuo Fu, Exploiting low cost reliability for NoC transient routing error, 3rd International Conference on Computer Technology and Development (ICCTD), 2011

7.Xiangming S, Yuzhuo F, Jiajia J, et al. Configurable Redundant Routing for Network on Chip[C]//Computational Intelligence and Communication Networks (CICN), 2012 Fourth International Conference on. IEEE, 2012: 477-479.

8.Jiao J, Fu Y, Jiang J. Architecture-level analysis and evaluation of transient errors on NoC[C]//NORCHIP, 2011. IEEE, 2011: 1-4.

9.Jiajia Jiao and Yuzhuo Fu. 2011. B2RAC: a physical express link addition methodology for network on chip. In Proceedings of the 4th International Workshop on Network on Chip Architectures (NoCArc ’11). ACM, New York, NY, USA, 17-22.

10.Jiajia Jiao; Yuzhuo Fu; Ting Liu; Han Wang; Xing Han; Jiafang Wang, “Performance analysis and optimization for homogenous multi-core system based on 3D Torus Network on Chip,” NEWCAS Conference (NEWCAS), 2010 8th IEEE International, pp.313,316, 20-23 June 2010

11.穆静,付宇卓,刘婷,. 片上网络中3D拓扑结构的性能评估[J]. 信息技术,2010,(5).

12.Jiajia Jiao; Yuzhuo Fu; Yaoyi Wu, “Multi-application Specified Link Removal Strategy for Network on Chip,” Computational Sciences and Optimization (CSO), 2011 Fourth International Joint Conference, pp.520,524, 15-19 April 2011

13.Han Wang; Yuzhuo Fu; Ting Liu; Jiafang Wang, “Thermal management via task scheduling for 3D NoC based multi-processor,” SoC Design Conference (ISOCC), pp.440,444, 22-23 Nov. 2010

14.Wenqi Bao; Jiang Jiang; Yuzhuo Fu; Qing Sun, “A reconfigurable macro-pipelined systolic accelerator architecture,” Field-Programmable Technology (FPT), pp.1,6, 12-14 Dec. 2011

15.Nanxiang Mei; Yuzhuo Fu; Ting Liu, “Distributed Shared Memory Architecture for NoC-Based Multi-Processor,” Computational Intelligence and Software Engineering(CiSE), pp.1,4, 11-13 Dec. 2009

16.Jiang Wang; Yuzhuo Fu; Liang Dong, “Modeling of UHF voltage multiplier for radio-triggered wake-up circuit,” . IEEE 10th Annual Wireless and Microwave Technology Conference (WAMICON ), pp.1,3, 20-21 April 2009